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HiWIRE II is provided in four segments:
This bulletin describes features added since the February 1993 printing of the HiWIRE II User's Guide. The date of your manual may be found on page ii on the top line with the copyright notice. Please insert this bulletin after the Updates tab in your manual.
Table of Contents
HiWIRE's plotting programs have been improved to allow color printing and plotting with colored pens. Although plotters behave differently from printers and the results are somewhat device-dependent, this feature can sometimes be useful for PCB checkplots or to highlight certain critical features in your schematic drawing. And, composite artwork (including negative layers) can readily be printed.
HiWIRE understands up to eight colors: Red, Green, Blue, Cyan, Magenta, Yellow, White, and blacK. These colors are abbreviated by their first letter (except for black which uses its final K). When you specify the layers to be printed or plotted, you can also specify their color by appending a letter to each layer number.
For example, 0R,1G specifies layer 0 should be drawn in red; layer 1 should be drawn in green. For compatibility, if the color is omitted, K is assumed.
On devices that support it (e.g., dot-matrix and laser printers), the background color can also be specified by a solo color letter that precedes all the layers. Thus K,0W,1W specifies that layers 0 and 1 are to be drawn in white upon a black background. If the background color is omitted, W is assumed.
Plotters simply draw the layers in sequence and their ink mixes or smears where objects overlap. This property is seldom useful.
Printers draw the layers opaquely in the order they appear in the list. Thus 0R,1G will first draw layer 0 in red then layer 1 in green. Green, layer-1 objects will obscure red ones on layer 0. This can be a useful property for printing composite artwork (e.g., the sort described in Section 21.3, Power Planes). K,248W,0,246 is typical for power-plane artwork. First, the layer-248 insulating areas are drawn in white into a black background. Next, layer-0 pads and layer-246 bridges are superimposed in the default black to complete the image.
0,1,253W after Add holes to circuit board... is the best way to print pad-holed artwork. First, solid pads and traces for the solder-side are drawn; afterwards, the layer-253 holes erase the pad centers.
A pen plotter can typically accept a variety of pen widths and colors in its various stalls. In the pen-definition file, you must tell HiWIRE the width and color of each available pen. In addition to the penno and pensize parameters described in Section 22.8, Pen-Definition Files, each line can specify a color for the pen. If color is omitted, K is assumed. For example:
# A Sample pen-definition file 1 0.6m G 2 0.3m Csays that a 0.6 millimeter-diameter green pen resides in stall 1; a 0.3 millimeter cyan pen is in stall 2.
In this version of HiWIRE, autoplace is implemented by seven cooperating programs. The executive, HW2.EXE, oversees the process and provides for seamless "point-and-click" operation. The bill-of-materials script, BM.D, extracts a packaging list from your schematic that specifies a footprint to use for each component. The footprint loader, FL.EXE, automatically loads footprints into your PCB and changes the generic site names (e.g., Unnn) to specific names that agree with your schematic.
The drawing analyzer, AN.EXE, examines your PCB, notes components you've manually positioned, finds the extent of each cell and the location of each net within it, and produces a special drawing that summarizes this information. The actual autoplace program, AP.EXE, rearranges this special drawing to facilitate cell interconnection. A post-processing script, PAP.D, rearranges the original PCB file using the positions suggested by the autoplacer. Finally, the sort program, SD.EXE, prepares the drawing for autorouting.
You can intervene at various stages in the placement process. After the components have been automatically loaded from the library, you can manually position some components (e.g., I/O connectors). You can define blocks of components you want placed together. You can specify allowable operations for each component such as rotation or flipping surface-mount components to the solder side of the board. If snap is enabled, the components will be snapped-to-grid if possible.
AP.EXE and PAP.D are included in the optional autorouter packages AR and ARX; all other programs and utilities are included in the basic HiWIRE EDT package so you can use their features even if you elect to forgo the autorouter.
In general, the best way to use the footprint loader is to include packaging information for each component in your schematic. However, FL will prompt you for the name of the footprint to use for any site that does not contain packaging information.
To specify the packaging for a component in the schematic, the component's schematic symbol must include a label with an attribute of pkg whose text field specifies the name of the PCB footprint. Since many components can be obtained in a variety of packages, Wintek's library symbols don't contain this packaging information.
Although you can use EE's Etc/ChgG and Lab commands to add this information to your schematics, a better alternative is to create a custom library containing the schematic symbols with packaging information for the components stocked by your company. See Section 14.3, Creating and Modifying Libraries, in the User's Guide.
| WARNING: If you decide to add packaging information to the existing HiWIRE libraries, we recommend that you rename these files so that subsequent HiWIRE upgrades do not destroy your work. |
You can add packaging information to these components to reflect your current practice. To keep this information from appearing on plotted drawings, put these pkg-attribute labels on a distinctive layer or make them invisible.
For a list of packages provided with the standard Wintek PCB.LIB, see Appendix O, Section O.8, PCB Library, in the User's Guide.
Before you use the footprint loader, you must define your board outline. If you will be using the placement optimizer, you must define the area within which AP will arrange your component footprints. This latter outline may be the same or may be a subset of the total board area.
You simply outline the perimeter of your board with layer-253 traces. If you are planning to mass-produce your design, you should probably use 93- or 98-mil traces. For more information, see the comments at the beginning of the DE script RT.D, and section 21.5, Creating a CNC-Mill Tape, in the User's Guide.
To reserve space for board cutouts, mounting holes, etc., surround them with 0-width lines on layer 253. (These lines will be ignored by RT.D when it creates the CNC milling tape.)
Once you have the board outline defined, set the grid to a suitable value for your components (e.g., 25 or 50 mils) and enable snap to force components to be placed on-grid.
To automatically load footprints into your drawing from Wintek's PCB.LIB, select Autoplace a circuit board... from the Main menu. Next, choose the schematic drawing for your design, the drawing containing the board outline, and the name of the library containing the component footprints. (A netlist is not required to load footprints.) Finally, select Load footprints from library.
The executive will run BM.D to extract a packaging list telling which footprint to use for each of your components. Next, it runs FL.EXE to load the required footprints. If you fail to provide packaging information for some of your components, FL allows you to intervene. It asks for the names of missing footprints and checks your response against the library names.
If FL can't match your response it assumes you typed a pattern which can include wildcard characters: ?, matching any character, and *, matching any string of characters. FL prints an array of choices that fit your pattern. FL's pattern matching is case-insensitive, so dip* matches DIP6, DIP8, DIP14, etc. If you prefer, you can also use a regular expression instead of a pattern. Just enclose it in slashes (/). See Section 29.12, Writing Regular Expressions in the User's Guide.
Needless to say, when you add footprints to Wintek's PCB library, avoid using names that contain /, ?, and *.
When FL loads footprints, it places them above the circuit board, ready for you to move onto the board, or ready for optimization by AP.
Sample files that you can use are located in the tutorial project:
1. If the current project isn't tutorial, select Change project... from the Main menu, and click on tutorial.
2. Autoplacement modifies the drawing file you use as the starting
point. In this step, you'll make a copy of BARE.PCB so
you'll have it in the future to use as a model. Use DOS to make
a copy of the file BARE.PCB: Select Other utilities...
from the Main menu, then Temporarily run DOS.
At the DOS prompt, type:
C> copy bare.pcb f.pcb
C> exit
3. Select Autoplace a circuit board... from the Main menu. Next, choose D.SCH for the schematic, F.PCB for the circuit board, and PCB.LIB for the library. (A netlist is used for optimizing the placement, but is not required to load footprints.) Finally, select Load footprints from library.
4. When the executive finishes running BM.D, FL.EXE, and SD.EXE, you may examine the file F.PCB with the editor. Those components that were loaded by FL are now located above the circuit-board outline.
By default, AP performs only translation of your footprints to fit them onto your board and places each component individually. You may want to allow a more liberal set of operations (e.g., rotation or surface-mounting on the solder side). You may want to preplace some components (e.g., I/O connectors) or to force a set of closely related components (e.g., a memory array) to be placed as a block.
To control these operations, edit the drawing containing the board and preloaded footprints. The location of the footprints with respect to the board outline determines how AP is allowed (or not allowed) to move each footprint. Components inside the board outline will not be moved; components above the board extent will not be rotated; components below the board can be rotated; and SMD components to the left or right of the board can be flipped and rotated.
Since FL loads all footprints above the board, the default allowed operation is moving the component without rotation or placement on the solder side. If you wish to change the allowed operations for a footprint, simply Mov it to the appropriate position.
The regions and the operations they allow are summarized graphically below. The diagram shows an irregularly shaped board outlined by 98-mil lines. It delineates the five regions described above:
If you want to force a set of components to be placed together, simply Etc/Bind them together. AP will place them as a unit, but will not modify their relative positions. The operations allowed on the unit follow the rules for individual components described previously. Since AP considers each unit (footprint or group of footprints) to have rectangular extent, avoid defining L- or U-shapes; as their interior space will be wasted.
After you have completed the previous steps, select Autoplace a circuit board... from the Main menu. Now choose the netlist for your design and the drawing containing the board outline. (Neither the schematic nor the library are required for this step.) Finally, select Optimize footprint placement.
The executive invokes AN.EXE to preprocess your drawing into a form suitable for use by AP. Next AP.EXE processes the information and derives an optimum placement where highly interconnected components are placed near each other. The DE script PAP.D transfers the optimization back to your original drawing. Finally, SD.EXE sorts the resulting drawing.
Continuing the example from before:
5. You'll need the netlist D.HNL for the schematic D.SCH to optimize the placement. To create this netlist, select Extract a netlist... from the Main menu, and click on D.SCH.
6. Select Autoplace a circuit board... from the Main menu. Choose D.HNL for the netlist and F.PCB for the circuit board. (A schematic and library are required to load footprints, but not to optimize their placement.) Finally, select Optimize footprint placement.
7. When the executive finishes running AN.EXE, AP.EXE, PAP.D, and SD.EXE, you may examine the file F.PCB with the editor. All of the components have been placed on the board.
New in version 2.3r0, power-plane routing is implemented as a series of pre- and postprocessing steps to conventional (signal) autorouting performed by AR.EXE or ARX.EXE. Six cooperating programs perform the overall autorouting steps:
PR.D is the power-plane autorouter. It reads your netlist and design rules that together specify the component pins you want connected on power planes. It then adds any necessary bridges and vias to your unrouted PCB to make the power-plane connections. PR also generates a temporary netlist with power-plane nets removed so they won't be connected again on the signal layers. PR uses a heuristic that blindly makes connections between the specified pins and their power planes. Fortunately, such connections rarely collide with each other or with neighboring footprints.
AN.EXE is the drawing analyzer. It reads PR's reduced netlist, your design rules, and the partially routed PCB. It analyzes signal and power-plane layers and catches occasional errors made by PR. AN generates a drawing file which specifies the existing and missing signal-layer connections for the design.
CRL.D changes the routing layers specified by AN's output drawing to disallow signal traces on the power layers.
AR.EXE (or ARX.EXE) is the signal-layer autorouter. It emits a drawing containing only its interconnecting traces and vias.
MPL.D moves the power layers as it merges AR's output into your unrouted board. So that AN could easily check them, PR's power-plane connections were put on the wrong layers. MPL moves them back where they belong.
HW2.EXE, the executive, coordinates the process. It runs the other programs as required to perform power-plane and signal-layer routing.
To specify the nets you want routed on power planes, add a label to your design-rule file. Put plane (not PLANE or Plane) in the label attribute; put the names of the power-plane nets in the label text. For example, to connect nets Vcc and gNd on power planes instead of signal planes consider the following portion of a design-rule file:
(+12 -12) 25 8 b 8 8 a Vcc gNd
Here rule-attribute labels force nets +12 and -12 to be connected on the signal layers with 25-mil (0.025") traces and others to be connected with 8-mil (0.008") runs. The third plane-attribute label commits its nets to internal power planes.
When you specify the Number of layers to autoroute, be sure to include the power planes. The number of signal layers available to the signal router is the total number of autorouting layers reduced by the number of power planes.
By default, PR.D uses 10-mil (0.010") traces to bridge a 10-mil (0.010") insulating gap. Your default design rules should allow this width and spacing, or you'll be forced to sift through a lot of width and spacing violations. Or, since PR.D is a text file, you can also change these defaults.
The details for using both the DOS autorouter, AR.EXE, and the Windows autorouter, ARX.EXE, have not changed. A step-by-step procedure can be found in Section 20.4, Invoking the Autorouters, in the HiWIRE II User's Guide.
Now though, PR.D is a potential new source of errors (e.g. shorts and/or width and spacing violations) which you must manually correct before autorouting can continue.
You should always check the autorouted result before you have your board manufactured. Use the same design rules that you used for autorouting.
Unfortunately, AN.EXE does not understand the composite imaging used to synthesize power-plane artwork. (In fact, theory asserts it can never reliably perform such an analysis.) Thus you must check the power-plane connections yourself.
When you Design-rule check a circuit board with power-plane connections you should get an open net for each pin connected to a power plane. Edit your PCB, and use Etc/Errs to visually confirm each connection. Press + to rapidly advance through all the connections.
What are the problems that can occur? Certainly any bridges you manually created (or PR.D automatically inserted) could be misplaced. However, a more subtle problem occurs when a conspiracy of vias forms around the bridge footing:
In the example, evil vias have penetrated the power-plane and eroded the bridge footing. They can cause width violations, or (as in the example) completely isolate the pin from its power plane.
Prior to V2.2r0, HiWIRE allowed only the minimum standard character set (decimal values 32 through 126) in drawing labels. With this new version, you can include labels in your drawings from eight-bit character sets with character values from decimal 32 through 255. The default character set is English, code page 437, but six additional character sets are included with this release:
| Code Page | Name |
|---|---|
| 850 | Multilingual Latin I |
| 852 | Slavic Latin II |
| 860 | Portugal |
| 863 | Canadian-French |
| 865 | Nordic |
| 932 | Japanese |
The default English code page includes some letters with accents, symbols, and Greek letters that you may find useful in your schematics, including mu, omega, beta, and plus-or-minus:
Other character sets include additional letters with various accents needed for non-English language words. None of the character sets include "line drawing" characters. Unimplemented characters will appear as a five-sided polygon (shaped like baseball's home plate). To examine all the characters available in a character set, you can view or print the Generic Drawing CT.DWG in the Tutorial project.
To choose a character set, select Change setup... from the Main menu, then choose Select character set.... A list of available character sets will be displayed. Click on the character set you wish to use.
To include a special character in a label, simply type the desired key. If your keyboard does not support the character you wish to use, you can enter the decimal value of the character using the numeric keypad. Either use the NUM LOCK key or hold the SHIFT key so that the keypad will produce numbers. To enter a special character, press and hold the ALT key, type the decimal value of the character, then release the ALT key. For example, to enter an omega (for ohms) in a label while using the English, code page 437, character set, press and hold the ALT key, type 234 on the keypad, then release the ALT key.
If you send your HiWIRE drawings to a service bureau for plotting, make sure you specify the character set to be used when plotting. NOTE: If you create Gerber files for the service bureau, HiWIRE converts all characters to strokes in the Gerber data, so you have complete control of the character set used. You do not need to notify the service bureau of the character set being used when you create the Gerber data.
The new, expanded character sets are not implemented for either the CGA or Hercules drivers.
The software for producing Gerber plot files has been improved
in V2.3r0. The following three commands on the Custom menu:
Photoplot a 2-layer PC board...
Photoplot a 4-layer PC board...
Photoplot a 6-layer PC board...
have been replaced with a single menu choice:
Generate Gerber/CAM files...
Please note this change on page 23-15 in the User's Guide.
The new software automatically determines the number of signal layers in your design, and infers the existence of silkscreens, power-planes, drilling and milling information, and surface-mount components. It will automatically create the aperture file, plot all of the signal layers, silkscreens, power planes, solder masks, and solder-paste masks, create drill and CNC mill tapes, produce a README file, and convert the Gerber plots back to a HiWIRE drawing for checking.
Before creating the Gerber plot files, make sure you've added the holes to drawing using the Add holes to a circuit board... command on the Other utilities menu, as discussed in Section 21.4, Creating a Drill Tape, in the User's Guide. If you also want to create a CNC mill tape, make sure you've added the milling information to layer 253 as described in Section 21.5, Creating a CNC-Mill Tape.
To create the Gerber and CAM data files for your design, place a blank diskette into a drive on your machine, and select Generate Gerber/CAM files... from the Custom menu.
Select the drawing to be plotted, then click on Generate Gerber/CAM files. The DE script CAM.D will ask you to choose between normal and one of two extended, embedded-aperture formats. If your vendor accepts either of the extended formats, choose it to minimize the chance of errors by the photoplotter operator.
Next, it will prompt for the drive that holds the blank diskette for the resulting CAM data and README file. If you suspect the files won't fit on a single floppy, just press ENTER to place them in the current project directory on your hard drive.
Once CAM.D and its batch file CAM2.BAT finish, all of the data files will have filenames GERB with numeric file extensions for the various Gerber plot files, and file extensions of .DRL and .CNC for the drill and CNC-mill tapes. The information file with a description of each file and the apertures used will be named README. Check the results carefully by viewing the file GERBVIEW.PCB with the HiWIRE editor. If it looks correct, send the diskette with the README file and all the GERB.* files to your service bureau.
To modify the operation of this command, make a copy of CAM.D and place the copy in your project directory. CAM.D can be edited to force the use of a fixed aperture file, and to change the annular rings produced for solder masks or power planes. See the comments at the front of the file for additional information by selecting Display a DE script... from the Other utilities menu, then click on CAM.D.
New video drivers have been included with this release. The standard VGA (640x480 pixels, 16 color) driver, VGA.VDR, is considerably smaller and faster than it was. Similar improvements have been made to the 800x600 super-VGA drivers.
A new 1024x768 super-VGA driver, VGA1024.VDR, has been added. This driver is not recommended for schematics. It should be very useful for PCB layouts if you have a 17" or larger monitor. This driver will only work on some video cards that support super-VGA. In particular, the CRT monitor, video card, and BIOS must support 1024x768 resolution, 16 colors, the VESA BIOS call for this mode, and a 128 KB video map.
The driver that was called VESA800.VDR in earlier versions of HiWIRE has been renamed VGA800.VDR. Please note this change on page E-3 in the User's Guide. If you have an earlier version of HiWIRE, please delete the driver VESA800.VDR from the HiWIRE EXE directory (usually C:\HW2\EXE).
With V2.3r0, both CONFIG and EP support two separate initialization strings for output devices. For printers like the HP LaserJet and the Canon Bubble Jet, this means HiWIRE can now form an initialization string that depends on both the desired resolution and the paper size. If you use either of these printers, you may wish to create a new configuration file to allow the use of paper sizes other than the standard 8.5-by-11 inches.
Support for printing invisible labels (i.e., size 0 labels) was removed from the software in Version 2.0r3 when the plot optimizer, PO.EXE, was added to the HiWIRE. Beginning with Version 2.2r0, this support has also been removed from the CONFIG and EP programs. Please delete this option from page 22-9 in the User's Guide.
The DE script PL.D can be used to toggle the size of invisible labels from size 0 (invisible) to size 4 (visible) and back. This can be used to view the pin labels of PCB footprints while editing a layout, and can be used to print drawings with invisible labels made visible. See the comments at the front of the file for additional information by selecting Display a DE script... from the Other utilities menu, then click on PL.D.
The plotting of pads with holes for pen-and-ink plotters and photoplotters is now handled by PO.EXE. For these devices, PO converts the pads to 8-14 line segments with a hole that is approximately one-third of the diameter of the smaller of the height or width of the pad.
Holed pads are not normally used for production circuit boards, but they are often invaluable for in-house, hand-drilled prototypes. As such, PO's approximation of the pad perimeter is close, but not exact. Also note that PO's approximation begins to develop spurious slots when the pad aspect ratio exceeds 5:3. None of the footprints in Wintek's PCB.LIB violate this limitation.
Pad holes for dot-matrix and laser printers are still handled by EP, and will be approximately 20 mils in diameter (at scale equal to 1). Because these holes are created using "white ink", they should not be obscured by traces that pass through the center of the pad. For output produced using pen-and-ink plotters and photoplotters, you must avoid passing a trace through the center of a pad to prevent the hole from being filled.
PO's new -h option decomposes pads into traces, but the executive makes this new feature transparent. Notice that unlike EP, PO restricts holes to layer-0 pads. This assures that surface-mount pads won't be holed, but it precludes through-hole footprints with different pads on opposite sides of the board.
EP.EXE and PO.EXE now support the embedded layer/color specification previously described.
PO's new -z option formerly merged colinear lines on different layers for more efficient plotting; this is now the default behaviour. Such merging is prohibited only if color plotting is specified by one or more color letters in the layer list.
When you convert a HiWIRE drawing to AutoCAD's DXF format, the DE script DXF.D will prompt with the question Basic or Advanced (B/A)? The Advanced format uses polylines to create traces with rounded endcaps and better round and oval pads. The Basic format is identical to earlier implementations in HiWIRE and should work with CAD packages that do not support polylines. See the comments at the front of the file for additional information by selecting Display a DE script... from the Other utilities menu, then click on DXF.D.
The footprint library, PCB.LIB, now includes footprints for the newer Quad Flatpack LSI packages.
The original drawing borders library, BORDERS.LIB, contains standard-size borders scaled for use with schematics and generic drawings that include size 1 labels.
An additional borders library, BORDR1X.LIB, contains the same drawing borders, but scaled for use with PCB and generic drawings with a scale of 1 (actual size).
When you Extract a netlist... (from the Main menu),
you can now choose the output format from the following list:
EDIF 2 0 0
FutureNet
HiWIRE II (normal)
PADS-PCB
PCAD Nets
Protel
Schema
smARTWORK (the original HiWIRE V1.0 format)
Spice
Susie (HiWIRE II hierarchical format)
Tango
All HiWIRE programs require the default HiWIRE II (normal) format, but the other netlist formats may be useful when you use HiWIRE with other CAD systems.
The Spice selection replaces the Spice input... choice on the Custom commands menu. Please make a note of this change on page 17-8 of the User's Guide.
Several new utilities written as DE scripts are included with this release of HiWIRE:
Additional information on the use and operation of these DE scripts can be found in the comments in the scripts. To view these comments, select Display a DE script... from the Other utilities menu, then click on script name.
Prior to V2.2r0, the stream-oriented Drawing Editor, DE, wouldset all variables to NIL before it began to execute a script. The newest release supports variable initialization. You can tell DE to initialize variables to a non-NIL constant in your script.
More importantly, you can also set variables from the command line, and use these variables to control the behavior of your script. Previously this control was handled by prompting for a needed value (e.g., BM.D's Text or DIF format (t/d):). It is difficult to use a prompting script in a batch file; it's impossible to prompt in a script that reads a text file.
In your script, anywhere you declare a variable, you can substitute an initializing expression for the variable name. The initializer must be a simple constant (e.g., a numeric constant, a string, or a regular expression); more complex expressions are not allowed.
For example:
variable ncol = 70, nlin = 60;
func() {
variable message = "A string";
:
}
main() {
func();
:
}
is exactly equivalent to:
variable ncol, nlin;
func() {
variable message;
message = "A string";
:
}
main {
ncol = 70; nlin = 60;
func();
:
}
Initializing variables in your script allows better localization of control. In our example, we set printer page-size parameters in one line rather than spread this action over two widely separated portions of the script.
On the command line, anywhere you can place a drawing name, you can also write an assignment of the form:
variable=constant
After performing initialization you specify in your script, DE will scan the command line and perform command-line assignments. Assignments that follow drawings will be deferred until the preceding drawings have been read. Only global variables can be set from the command line.
For example suppose there's a variable pass in your script READ2.D that reads a drawing ABC.PCB twice. The following invocation allows your script to distinguish items read during each pass:
de read2.d pass=1 abc.pcb pass=2 abc.pcb
In our example, constant was a numeric constant. Although regular expressions, character constants and string constants are also allowed, the command-line processor may molest them. Specifically, unless they're protected with a backslash (\), all single and double quotes (" and ') and backslashes are removed. The following example sets a global variable in the new BM.D script to the string "part":
de bm.d key=\"part\" mydwg.sch
Some of the scripts included in V2.3r0 have been modified to take advantage of these new features. See BM.D and CN.D for more examples of how variable initialization and command-line assignment can be used.
The wildcard characters ? and * can now be used in filenames on the command line.
Corrupt drawing file handling has been improved so that MERGE.D can be used to recover the undamaged portion of the file.
The -i option can be used as an alternative to the DOS standard-input redirection character <. For example:
de cn.d fmt=3 -itest.hnl
The Generate a Bill of Materials command on the Other utilities menu now supports extracting a netlist from all schematics in the project.
Until V2.2r0, the bill-of-materials processor, BM.D, could only produce hierarchical BOMs. If you used a resistor in a functional block, that resistor was listed only once even if there were 20 instances of the block in your design.
If BM.D discovers your design is hierarchical, the new script offers the option of a flat bill of materials. In a flat BOM your resistor would be listed 20 times with distinct nested sitenames identical to those in a flattened netlist.
Mainly in support of autoplace, BM.D will now generate an abbreviated format. This format is easier for a machine to read. There is no pagination and no page or column headings. Each line in an abbreviated BOM specifies a single key property of each component. For example:
de bm.d key=\"pkg\" mydwg.sch
extracts only the contents of pkg-attributed labels. Other labels (e.g., those whose attribute is value or vendor) are ignored.
A new option for AN.EXE has been added to support the placement optimizer, AP:
l - generate an input file for the placement optimizer, AP.EXE.
The autoplacer, AP, reads a layout file generated by the drawing analyzer, AN. It devises an optimum arrangement of the components in your design intended to minimize the difficulty of their interconnection.
AP is invoked as follows:
ap layout
where layout is the intermediate file generated by AN using the l option.
After AP has arrived at an optimum arrangement, the script PAP.D applies the result to your original drawing file.
For information on using AP from the executive program, see the section Autoplace Utilities Added to HiWIRE in this Technical Bulletin.
HiWIRE's footprint loader, FL, reads a packaging list that specifies each component in your design and the library name of the object (i.e., footprint) you want used to represent it. Typically, the packaging list is generated from your schematic by the bill-of-materials utility.
You also specify a drawing file and a set of libraries. FL scans the libraries for the named objects and adds them to your drawing; generic labels (e.g., Unnn) are changed to specific names as specified by the packaging list.
FL is invoked as follows:
fl [options] packlist drawing library(s)
where options include:
-eerrors - emit diagnostics to file errors instead of to the screen and silently load only those footprints in the packaging list and found in the libraries.
-aassembly - load footprints for the named assembly instead of the nameless root assembly.
Required FL parameters are:
packlist - a text file that specifies footprints to be loaded.
drawing - a HiWIRE drawing file to which the footprints are to be added.
library(s) - Names the libraries to scan for footprints. Libraries are scanned in the order specified on the invocation line. FL first tries to find each library in the current directory. If that fails, it next tries the directory containing the HiWIRE libraries (specified by HW2_LIB in the setup data file). If you use a normal HiWIRE drawing instead of a library, the entire drawing will be treated as a footprint with that name.
Each line in the packlist file contains three blank-separated fields:
[part] site footprint
In hierarchical designs, the first field specifies the name of the assembly holding the component named by the second field. The first field is omitted in flat designs or for the root assembly in hierarchical designs. The third field specifies the name of the library object to be used for the component. Some examples:
U100 PGA68
MEM U35 DIP28
The first line specifies that U100 in the root assembly is housed in a 68-pin-grid-array package. The second line reveals that U35 in subassembly MEM uses a 28-pin DIP package.
If footprint is omitted or can't be found, FL queries you for an appropriate package (unless the -e option is used). FL displays an array of choices and asks you to pick one. FL tries to match your response against the library names. If it can't, FL interprets your response as a "pattern" which can include wildcard characters: ? (matching any single character) and * (matching any string). FL displays a reduced set of choices that match the pattern; upper/lower case is ignored when FL performs pattern matching. From Wintek's PCB.LIB for example, dip* would list all the dual-inline packages; DIP? would list only those with fewer than 10 pins.
If an unmatched response begins with a /, FL treats it as a "regular expression" and uses it for a similar winnowing. For convenience, you may omit the trailing /. See Section 29.12 in the User's Guide, Writing Regular Expressions.
For information on using FL from the executive program, see the section Autoplace Utilities Added to HiWIRE in this Technical Bulletin.